LCD (liquid crystal display) apparatuses or organic EL display apparatuses are widely used due to their display performance, energy saving properties, and other such reasons. These display apparatuses constitute nearly all of the mainstream of display apparatuses, in particular, display apparatuses in cellular phones, PDAs (personal digital assistants), PCs, laptop PCs, and TVs. Generally, TFT substrates are used in these display apparatuses.
For instance, in liquid crystal display apparatuses, display materials such as a liquid crystal are filled between a TFT substrate and an opposing substrate. In these display materials, a voltage is selectively applied to each pixel. Here, a “TFT substrate” means a substrate on which a TFT (Thin Film Transistor) having a semiconductor thin film (also called “semiconductor film”) is arranged. Generally, a TFT substrate is referred to as a “TFT array substrate” since TFTs are arranged in an array.
On a TFT substrate which is used in a liquid crystal display apparatus and so on, “sets” (a set includes a TFT and one pixel of the screen of a liquid crystal display apparatus, called “one unit”) are arranged vertically and laterally on a glass substrate. In a TFT substrate, for example, gate wires are arranged at an equal interval in the vertical direction on a glass substrate, and either source wires or drain wires are arranged at an equal interval in the lateral direction. The other of the source wire and the drain wire, a gate electrode, a source electrode and a drain electrode are provided respectively in the above-mentioned unit constituting each pixel.
<Conventional Method for Producing TFT Substrate>
As the method for producing a TFT substrate, a 5-mask process using five masks, a 4-mask process using four masks by half-tone exposure technology, and other processes are known.
In such a method for producing a TFT substrate, the production process needs many steps since five or four masks are used. For example, the 4-mask process requires 35 steps and the 5-mask process requires steps exceeding 40. Such a many production steps may decrease the production yield. In addition, many steps may make the production process complicated and also increase the production cost.
(Method for Production Using Five Masks)
FIG. 54 is schematic cross-sectional views for explaining the conventional method for producing a TFT substrate, in which (a) is a cross-sectional view after formation of a gate electrode.
(b) is a cross-sectional view after formation of an etch stopper.
(c) is a cross-sectional view after formation of a source electrode and a drain electrode.
(d) is a cross-sectional view after formation of an interlayer insulating film.
(e) is a cross-sectional view after formation of a pixel electrode.
In FIG. 54(a), a gate electrode 9212 is formed on a glass substrate 9210 by using a first mask (not shown). That is, first, a metal (such as aluminum (Al)) is deposited on the glass substrate 9210 by sputtering. Then, a resist is formed by photolithography by using the first mask. Subsequently, the gate electrode 9212 is formed into a predetermined shape by etching, and the resist is removed through an ashing process.
Next, as shown in FIG. 54(b), on the glass substrate 9210 and the gate electrode 9212, a gate insulating film 9213 formed of an SiN film (silicon nitride film) and an α-Si:H(i) film 9214 are stacked in this order. Subsequently, an SiN film (silicon nitride film) as a channel protective layer is deposited. Then, a resist is formed by photolithography using a second mask (not shown). Then, the SiN film is patterned into a predetermined shape by a dry etching method using a CHF gas, an etch stopper 9215 is formed, and the resist is removed through an ashing process.
Next, as shown in FIG. 54(c), an α-Si:H(n) film 9216 is deposited on the α-Si:H (i) film 9214 and the etch stopper 9215. Then, a Cr (chromium)/Al double-layer film is deposited thereon by vacuum deposition or sputtering. Subsequently, a resist is formed by photolithography using a third mask (not shown). Then, the Cr/Al double-layer film is patterned by an etching method, whereby a source electrode 9217a and a drain electrode 9217b are formed in a predetermined shape. In this case, Al is patterned by a photo-etching method using H3PO4-CH3COOH-HNO3 and Cr is patterned by a photo-etching method using an aqueous solution of diammonium cerium nitrate. Subsequently, the α-Si:H films (9216 and 9214) are patterned by a dry etching method using a CHF gas and a wet etching method using an aqueous hydrazine solution (NH2NH2.H2O), whereby the α-Si:H (n) film 9216 and the α-Si:H (i) film 9214 are formed in predetermined shapes, and the resist is removed through an ashing process.
Next, as shown in FIG. 54(d), before forming a transparent electrode 9219, an interlayer insulating film 9218 is deposited on the gate insulating electrode 9213, the etch stopper 9215, the source electrode 9217a and the drain electrode 9217b. Subsequently, a resist is formed by photolithography using a fourth mask (not shown). Then, the interlayer insulating film 9218 is patterned by an etching method, a through hole 9218a for electrically connecting the transparent electrode 9219 with the source electrode 9217a is formed, and the resist is removed through an ashing process.
Next, as shown in FIG. 54(e), on the interlayer insulating film 9218 in a region where patterns of the source electrode 9217a and the drain electrode 9217b are formed, an amorphous transparent conductive film formed mainly of indium oxide and zinc oxide is deposited by sputtering. Subsequently, a resist is formed by photolithography using a fifth mask (not shown). Then, the amorphous transparent conductive film is patterned by a photo-etching method using an approximately 4 wt % aqueous solution of oxalic acid as an etchant. Then, the amorphous transparent conductive film is formed in such a shape that the film electrically contacts the source electrode 9217a and the resist is removed through an ashing process. Whereby the transparent electrode 9219 is formed.
As mentioned above, five masks are required in the conventional method for producing a TFT substrate.
(Method for Production Using Three Masks)
To improve the above-mentioned conventional technology, various technologies to produce a TFT substrate by a method in which production steps are further reduced by decreasing the number of masks (from five to three, for example) have been proposed. For example, the following patent documents 1 to 7 describe a method of producing a TFT substrate using three masks.    Patent Document 1: JP-A-2004-317685    Patent Document 2: JP-A-2004-319655    Patent Document 3: JP-A-2005-017669    Patent Document 4: JP-A-2005-019664    Patent Document 5: JP-A-2005-049667    Patent Document 6: JP-A-2005-106881    Patent Document 7: JP-A-2005-108912